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About the Author

Danny Jiang is a seasoned system software engineer and technical lead with over 20 years of hands-on experience in firmware development, CPU/SoC architecture, and system validation. Currently serving as a Benchmarking/Application Engineer at SiFive, Danny has built his career working with leading semiconductor and processor companies, including MIPS (under Imagination Technologies, MIPS LLC, and Wave Computing), Broadcom, Western Digital, Andes Technology, and Silicon Integrated Systems (SiS).

Throughout his career, Danny has contributed to the development and deployment of millions of chips across diverse domains—from RISC-V and MIPS processors to SSD controllers, Bluetooth/IoT chipsets, and x86 chipset BIOS. His expertise spans the entire system software stack, from low-level bootloaders and device drivers to ASIC/FPGA validation and system integration.

Professional Expertise

Danny specializes in:

  • Processor Architecture: RISC-V, MIPS, ARM, x86

  • System Software: Bootloaders, firmware, device drivers, RTOS porting

  • Validation & Verification: ASIC/FPGA bring-up, silicon validation, system integration

  • Embedded Systems: IoT, SSD, wireless connectivity (Bluetooth, 802.15.x)

  • Performance Engineering: Benchmarking (CoreMark, Dhrystone), optimization

  • Customer Support: Technical troubleshooting, toolchain customization, training

Connect with Danny:

Other Works:

  • See RISC-V Run: Fundamentals (this book)
  • Various open-source contributions to RISC-V ecosystem

Acknowledgments

The author would like to thank:

  • RISC-V International and all contributors to the RISC-V specifications for creating an open, well-documented ISA
  • The RISC-V community for their collaborative spirit and commitment to open standards
  • Colleagues and mentors at SiFive, MIPS, Andes, Broadcom, Western Digital, and SiS for their insights and expertise
  • Early reviewers who provided valuable feedback on draft chapters
  • Family and friends for their unwavering support during the writing process

About the Book

“See RISC-V Run: Fundamentals” is inspired by Dominic Sweetman’s classic “See MIPS Run” and aims to provide the same level of comprehensive, systematic coverage for the RISC-V architecture. This book combines:

  • Rigorous technical accuracy based on official RISC-V specifications
  • Practical insights from real-world implementation experience across multiple processor families
  • Clear explanations suitable for students, engineers, and researchers
  • Comparative analysis with ARM and MIPS to build architectural intuition

This volume focuses on fundamental concepts—from ISA basics and programmer’s model to pipeline design, system software, and platform integration. Future volumes, including “See RISC-V Run: Advanced”, will explore microarchitecture optimizations, advanced extensions, and cutting-edge implementations.

The book is licensed under CC BY 4.0, reflecting the author’s commitment to open knowledge sharing, consistent with the RISC-V philosophy.

January 2026